Design of Humanoid and Drone Hybrid for Neutralizing Threats and Surveillance (A multipurpose humanoid system which could be useful in many applications including defense, surveillance and any hazardous working environment.)
Designed Mechanical structure for Arm, Head along with Drone. Xbee (S1) protocol has been used for human communication with drone through Flex and Accelerometer (ADXL335) sensor. ATmega328 was interfaced with ADXL335 Sensors and Xbee module. Mechanical designing of torque calculations and kinematics for robotic arms, rack and pinion etc.
Design and Development of a pressure control system for brace treatment of scoliosis (Bracing is a common nonsurgical treatment for scoliosis, in which the treatment which is used is not that effective in order to treat Adolescent Idiopathic Scoliosis (AIS) patients)
Designed a prototype Belt to apply and maintain appropriate pressure for scoliosis treatment. 10Bit ADC has been used to convert data from Pressure sensor (MPX5010) into Digital form. 6 volt Electric Diaphragm and solenoid valve used to exert pressure in Air bladder inside Belt. UART of MSP 430 was used to display the result and the system was designed, implemented and tested on MATLAB.
Sancharak Cellphone for Blind people
(Braille enabled cell phone for blind that can be used for managing calls, messages efficiently with various features for visually impaired) Designed a prototype mobile which has Braille enabled display, Braille QWERTY keypad, fast typing mechanism, battery level indicators and network indicators for visual impaired. Atmega 2560 has been used to control all output device ports, Micro-solenoid has been used to form Braille display of 20 characters. GSM module was interfaced with Atmega 2560 to receive calling and messaging data.
Eye-watch (Special Braille enabled watch for visually impaired)
Designed prototype with Atmega328/msp430g2553 to display timing with four character solenoid matrix. It has special functions such as Braille cell phone connectivity, emergency contact etc.
Design and implementation of stand-alone QNX Neutrino program to measure the distance between the rear bumper of your car and any objects behind the vehicle while parking.
The designed code is capable of collecting data from ultrasonic sensor and print the signal according to distance between rear bumper and the obstacle while car parking. HC SR04 ultrasonic sensor is used to sense data for detection and serial communication is used to print different alerts.
RTL Design of Sobel Edge Detection IP Core Spring 16
Designed a Sobel edge filter for edge detection of 256x256 pixel images using VHDL for FPGA/ASIC applications. Achieved performance of 112 MHz clock frequency and 18.4mW dynamic power, after generating layout and DRC and LVS check.
Design of a Standard Cell Library Spring 16
Created 45nm CMOS standard cell library using the Cadence Design Systems -IC Custom, full custom integrated circuit design environment with DRC and LVS verification.
Projects (Analog/ Mixed signal)
Schematic and physical layout design for 6 Bit pipeline ADC Spring 17
Designed 6 bit Flash ADC using two 3 bit flash ADCs which exhibits DNL < (0.5LSB) 3.90625mV, INL < (0.5LSB) 3.90625mV, Settling time < 100nsec, power consumption < 2mW with < 8000 um2 area budget using 45nm CMOS process and tested using test bench setup, Verilog-A over corners.
Designed circuits such as: Comparator, resistor ladder, 3 bit ADC, DAC, Unity Gain buffer, Subtractor using Cadence Virtuoso CAD design tool.
Designed physical design for resistors and converter circuit using poly resistors with clear DRC and matched LVS, physical design was optimized to save area and each block was placed according to heat profile. Implemented DAC block using Verilog-A to test designed 6 bit ADC.
Comparator design using cross coupled bi-stable current sources Spring 17
Developed comparator and obtained gain greater than 100 (40dB), Hysteresis between 10m V and 20mV, Power dissipation as 30uW and Propagation delays were under 12nsec. Transient and DC analysis were performed with test bench setup to obtain app specifications using Cadence Virtuoso tool at 45nm CMOS process. Equations used with inbuilt functions to perform simulations over corner cases using ADE-XL.
Implemented physical layout for comparator using common centroid and inter digitized techniques for matching and low offset.
Schematic and physical layout design for Low Noise CMOS Operational Amplifier Fall 15
Implementation of two stage differential amplifier with followed by cascode second stage was performed and achieve >80 db DC open loop gain, 65.77 MHz gain bandwidth product , with 3.07 V/ uSec slew rate, Performed stability analysis like Corners and Monte Carlo.
Common centroid physical layout technique is used to reduce all direction process variations and overall offsets at the input side of differential amplifier, performed DRC and LVS analysis for designed physical layout.
CMOS β-multiplier based constant-GM current reference current mirrors Fall 15
Designed and simulated CMOS β-multiplier based constant-gm current reference current mirror using 45 nm technology with stability analysis over temperature (Corners) to achieve constant current of 25uA at 1V supply.
Band Gap Reference Fall 15
Designed and simulated Band Gap Reference to have a temperature coefficient as low as 24ppm/°C in nominal case using generic 45nm CMOS process to generate a reference of 1V with stability analysis over temperature and voltage (Corners and Monte Carlo).
On-Chip Power Delivery Network (Grid & Spiral layout design and performance analysis) Spring 16
Designed Power delivery network for 20 mm chip at 0.18um technology using Mentor Graphics Pyxis tool to obtain performance parameters such as settling time, RLC response and step response. Modeled RLC equivalent model from layout simulations with mathematical calculations.
Compared and characterized Grid & Spiral layout design on the bases of operating voltage and frequency of operation.
Design, Fabrication and Test of a PMOS Transistor, PMOS Inverter and NAND GateFall 16
Fabricated a PMOS Transistor, PMOS Inverter and NAND Gate in RIT semiconductor fabrication lab. Implemented physical layout design using Mentor Graphics Pyxis Tool on 1um Technology node. Various Parameters of the design such as Oxidation level, Junction Depth, Oxide thickness were measured using simulation with Silvaco Athena tool and compared it with actual process measurement. Tested fabricated silicon chip on probe station and compared test results with hand calculations to observe process defects and variations.